/////////////////////////////////////////////////////
// File Name: mac_r_v1_tb.v
// Author: zeping fan
// mail:   zpfan007@163.com
// Created Time: 2023年06月08日 星期四 12时57分02秒
/////////////////////////////////////////////////////

module  mac_r_tb();

reg             clk;
reg             rst_n;
reg             rx_clk;
reg             rx_dv;
reg     [3:0]   rx_d;
reg             data_fifo_rd;
reg             ptr_fifo_rd;

wire    [7:0]   data_fifo_dout;
wire    [15:0]  ptr_fifo_dout;
wire            ptr_fifo_empty;

wire    [8*70-1:0] data_in;

assign  data_in = 'h0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210_0123456789abcdef_fedcba9876543210;
always #20  rx_clk = ~rx_clk;
always #5   clk = ~clk;

initial begin
    $fsdbDumpfile("mac_r.fsdb");
    $fsdbDumpvars(0,mac_r_tb);
    $fsdbDumpMDA();

    clk = 1'b0;
    rst_n = 1'b0;
    rx_clk = 1'b0;
    rx_dv = 1'b0;
    rx_d[3:0] = 4'b0;
    data_fifo_rd = 1'b0;
    ptr_fifo_rd = 1'b0;
    repeat(2) @(posedge rx_clk);#0;
    rst_n = 1'b1;
    repeat(2) @(posedge rx_clk);#0;
    rx_dv = 1'b1;
    for(integer i=0;i<3;i=i+1)begin
        rx_d[3:0] = 4'b1010;
        @(posedge rx_clk);#0;
    end
    rx_d[3:0] = 4'b1011;
    @(posedge rx_clk);#0;
    for(integer j=140;j>1;j=j-1)begin
        rx_d[3:0] = data_in[4*j-1-:4];
        @(posedge rx_clk);#0;
    end
    rx_d[3:0] = data_in[3:0];
    @(posedge rx_clk);#0;
/*
//crc_result= 32'hce5b5530
    rx_d[3:0] = 4'hc;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'he;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'h5;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'hb;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'h5;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'h5;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'h3;
    @(posedge rx_clk);#0;
    rx_d[3:0] = 4'h0;
    @(posedge rx_clk);#0;
*/    
 //   repeat(20)@(posedge rx_clk);#0;
    rx_dv = 0;



    #1000;
    $finish;
end




mac_r_v1#(
    .DATA_FIFO_DEPTH(4096),
    .PTR_WIDTH(11)
)
u_mac_r(
    .clk(clk),
    .rst_n(rst_n),
    .rx_clk(rx_clk),
    .rx_dv(rx_dv),
    .rx_d(rx_d),
    .data_fifo_rd(data_fifo_rd),
    .data_fifo_dout(data_fifo_dout),
    .ptr_fifo_rd(ptr_fifo_rd),
    .ptr_fifo_dout(ptr_fifo_dout),
    .ptr_fifo_empty(ptr_fifo_empty)
);

endmodule
